1. Field of the Invention
The present invention relates in general to the fabrication of semiconductor devices, and more particularly to a method for forming a landing plug contact in a memory device.
2. Description of the Related Arts
In DRAM fabrication, even though the DRAM technology is progressing, a simple rectangular pattern shown in FIG. 1A is being widely used for the active area formed by Shallow Trench Isolation (STI). However, there is a bitline and node contact (CB and CN) landing problem when using the simple rectangular active area pattern in the capacitor over bitline (COB) structure. An extended landing pad method and twisted bitline technology has been proposed to address the above problem, but they suffer from other problems. In the extended landing pad method, there is a photolithography limitation due to the close packed unsymmetrical contact pattern and small contact dimensions.
In the twisted bitline technology, the increased bitline-to-bitline coupling capacitance results in degradation of the retention time.
Recently, a method using an island-shaped mask pattern assisted by CMP is provided in "A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond", Y.Kohyama et al., Symposium on VLSI Technology Digest of Technical Papers, p. 17, 1997. It is explained in detail.
FIGS. 1.about.4 are views illustrating the steps of the method. FIGS. 1B.about.4B and FIGS. 1C.about.4C are the cross-sectional views derived by cutting FIGS. 1A.about.4A along the lines AA' and BB', respectively.
Referring to FIGS. 1A, 1B and 1C, a substrate 10 is provided, and active areas 12 and an isolation area 14 are formed thereon by STI with the simple rectangular active area pattern.
Referring to FIGS. 2A, 2B and 2C, by ion implantation, doped regions 16 are formed for the source and drain regions of the devices. Then, a gate oxide 18, a polysilicon layer 20, a metallic layer 22 and a nitride layer 24 are deposited sequentially. The gate oxide 18, polysilicon layer 20 and metallic layer 22 are 20 .ANG..about.50 .ANG., 500 .ANG..about.1500 .ANG. and 500 .ANG..about.1500 .ANG. in thickness, respectively. The metallic layer 22 used as wordline is composed of W or WSi.sub.2, the nitride layer 24 used as isolation layer is composed of SiN, and the polysilicon layer 20 is used as gate. Afterward, strip-shaped stacked layers 25 composed of gate 20 (the polysilicon layer), wordline 22 (the metallic layer) and isolation layer 24 (the nitride layer) are formed by conventional photolithography and etching. Thus, stacked layers 25 stretch over the active areas 12. Then, a covering isolation film 26 composed of SiN and an isolation layer 28 composed of BPSG are deposited. The isolation layer 28 is ground by CMP so that the isolation layer 28 and the stacked layers 25 have a joint plane surface.
In FIGS. 3A, 3B and 3C, the isolation layer 28 is etched with island-shaped rectangular patterns 30. The island-shaped rectangular patterns 30 stretch over the stacked layers 25 and mask the isolation layer 28 therebeneath during etching. Consequently, bitline contacts 32A and node contacts 32B are formed by self alignment contact etch technology and the bitline contacts 32A are longer than the node contacts 32B in length.
In FIGS. 4A, 4B and 4C, a conducting layer 34 composed of W or polysilicon is deposited and ground by CMP so that the conducting layer 34 and the stacked layers 25 have a joint plane surface.
The above method eliminates the problems in the extended landing pad method and twisted bitline technology, but results in a large leakage current and bitline-to-wordline coupling capacitance due to the long bitline contacts.